In general, active matrix liquid crystal display devices include a display section with two transparent substrates having a liquid crystal layer provided therebetween, one of which has a plurality of source bus lines as video signal lines and a plurality of gate bus lines as scanning signal lines, the source bus lines and the gate bus lines being arranged in a grid form, pixel formation portions being arranged in a matrix form at their corresponding intersections between the source bus lines and the gate bus lines. The active matrix liquid crystal display devices also include a source driver for driving the source bus lines in the display section and a gate driver for driving the gate bus lines in the display section.
FIG. 1 is a block diagram illustrating the configuration of a substantial part of a active matrix liquid crystal display device, along with an equivalent circuit in the display section. The liquid crystal display device includes a display control circuit 200, a source driver 300, a gate driver 400, and a display section 600. The display section 600 has provided therein a plurality (n) of source bus lines SL1 to SLn and a plurality (m) of gate bus lines GL1 to GLm, which (perpendicularly) cross each other. The source bus lines SL1 to SLn are connected to the source driver 300, while the gate bus lines GL1 to GLm are connected to the gate driver 400. In addition, a thin film transistor 60 (hereinafter, referred to as a “TFT 60”) acting as a switching element and a pixel capacitance 61 connected to the TFT 60 are provided at each intersection between the source bus lines SL1 to SLn and the gate bus lines GL1 to GLm. Each TFT 60 has a gate terminal connected to any one of the gate bus lines GL1 to GLm, a source terminal connected to any one of the source bus lines SL1 to SLn, and a drain terminal connected to the pixel capacitance 61. The pixel capacitance 61 is composed of a liquid crystal capacitance and an auxiliary capacitance (retention capacitance), the liquid crystal capacitance being a display medium provided between a pixel electrode, which is a transparent electrode, and a common electrode (counter electrode) provided opposite thereto, the auxiliary capacitance being provided in parallel with the liquid crystal capacitance.
For such a liquid crystal display device, there is a conventionally-known drive method called the “dot-sequential drive system” in which the source bus lines SL1 to SLn are sequentially driven one by one. According to this drive method, the source driver 300 sequentially applies a video signal to each of the source bus lines SL1 to SLn for a predetermined period of time. On the other hand, the gate driver 400 sequentially selects each of the gate bus lines GL1 to GLm for one horizontal scanning period in accordance with a horizontal synchronization signal HSY and a vertical synchronization signal VSY, which are outputted from the display control circuit 200, to bring the TFTs 60 connected to the selected gate bus line into a conductive state. As a result, the video signals applied to the source bus lines SL1 to SLn are sequentially written to the pixel capacitances 61 connected to the TFTs 60 that have been turned on. When the TFTs 60 on the selected gate bus line are rendered non-conductive, the charge of the pixel capacitances 61 connected to the TFTs 60 is retained until the video signal AV is written in the next frame period.
Incidentally, as for liquid crystal molecules included in the liquid crystal capacitances of the pixel capacitances 61 in the display section 600, when a direct-current voltage is applied thereto for a long period of time, polarization takes place, resulting in deterioration of properties. Accordingly, the voltage to be applied to the liquid crystal capacitances is generally inverted every frame period. Also, in order to enhance visual quality, a drive method called the “line inversion system” is employed, in which a voltage having its polarity changed every horizontal scanning line is applied to the liquid crystal layer. According to this drive method, the polarity of the video signal with reference to the potential of the common electrode (common electrode potential) is switched every horizontal scanning period. Note that such a change in polarity of the video signal with reference to the common electrode potential is referred to as “polarity inversion”. Examples of the methods for realizing the polarity inversion include a method in which only the potential of the video signal is switched every horizontal scanning period, while maintaining the common electrode potential at a constant level, and a method in which both the common electrode potential and the potential of the video signal are switched every horizontal scanning period. According to the latter method (hereinafter, referred to as the “line common inversion system”), the common electrode potential is switched between high and low potential levels every horizontal scanning period. In addition, the potential of the video signal is set as negative with respect to the common electrode potential when the common electrode potential is at high potential level, and positive when the common electrode potential is at low potential level.
FIG. 13 is a signal waveform diagram for the video signal AV in the conventional liquid crystal display device. As shown in FIG. 13, one horizontal scanning period includes a horizontal effective display period in which the video signal AV is outputted to any one of the source bus lines SL1 to SLn, and a horizontal blanking period in which no video signal AV is outputted to any of the source bus lines SL1 to SLn. Also, one vertical scanning period includes a vertical effective display period consisting of a plurality of horizontal scanning periods, and a vertical blanking period in which no video signal AV is outputted to any of the source bus lines SL1 to SLn. Note that during the vertical blanking period, the potential of the video signal AV is generally set at white level.
Looking now at individual pixels, the voltage to be applied to the liquid crystal layer is inverted every frame period. In the case where the aforementioned dot-sequential drive system is employed, a period in which the video signal AV is applied to each of the source bus lines SL1 to SLn is short. Therefore, in some cases, the source bus lines might not be charged sufficiently. As a result, for example, in the case of the normally-white liquid crystal display device, the black potential (i.e., the potential corresponding to a display of black) is not sufficiently written to the pixel capacitances 61 included in the display section 600, resulting in display faults such as contrast reduction.
For the aforementioned display faults such as contrast reduction, some methods have been disclosed, in which the source bus lines SL1 to SLn are pre-charged (preliminarily charged) at a midpoint potential of the video signal AV during the horizontal blanking period (e.g., Japanese Laid-Open Patent Publication No. 2-204718). According to these, the video signal AV is sequentially outputted to the source bus lines SL1 to SLn after charging the source bus lines SL1 to SLn at the midpoint potential during the horizontal blanking period. Therefore, compared to the case of not being pre-charged, it is possible to reduce the change of the potential of the source bus lines SL1 to SLn to be charged by the source driver 300. Thus, the aforementioned display faults are suppressed from occurring.
In addition, because the display section 600 includes a number of TFTs 60 in the pixel formation portions, and the TFTs 60 are extremely small, there is a problem where display defects (hereinafter, also referred to as “pixel defects”) readily occur during production of the active matrix liquid crystal display device. Examples of the display defects include generation of bright spots (bright spot defects) and generation of black spots (black spot defects), and in particular, the bright spot defects are extremely conspicuous and can be visually recognized as display faults. As shown in FIG. 13, the vertical scanning period includes the vertical blanking period during which a white level signal is generally outputted as the video signal AV. When a full-screen black display is presented by the liquid crystal display device, a black level signal is written and retained in pixel capacitances of pixel formation portions having no defects (hereinafter, referred to as “normal pixel portions”. On the other hand, as for pixel portions with leakage between the drain terminal and the source terminal due to poor properties of the TFT 60 (hereinafter, referred to as “faulty pixel portions”), a white level signal is written during the vertical blanking period due to the leakage as shown in FIG. 13, although a black level signal is written during the vertical effective display period. Accordingly, the average level of the voltage applied to the liquid crystal in the faulty pixel portions is lower than the levels of the voltage applied to the liquid crystal in normal pixel portions around the faulty pixel portions. As a result, in the normally-white liquid crystal display device, display brightness of the faulty pixel portions is higher than that of the normal pixel portions therearound, so that bright spots are generated. On the other hand, as for the normally-black liquid crystal display device, black spots are generated.
For the above-described problem, some methods are disclosed, in which the signal level of the video signal AV is set at black level, rather than at white level, during the vertical blanking period (e.g., Japanese Laid-Open Patent Publication No. 1-128098). According to these, because the video signal AV is set at black level during the vertical blanking period, the display brightness of the faulty pixel portions is equal to or darker than that of the normal pixel portions therearound, so that bright spot defects are visually less recognizable. Furthermore, there are disclosed some methods in which the vertical blanking period is prolonged, during which the video signal AV is set at black level, thereby making the display brightness of the faulty pixel portions closer to the black level (e.g., Japanese Laid-Open Patent Publication No. 6-141269).
In addition, when an open-mode fault occurs between the source terminal and the drain terminal in the TFT 60, no voltage is applied to that faulty pixel portion. Accordingly, in the normally-white liquid crystal display device, the faulty pixel portion always appears as a bright spot. Conventionally, to correct such a pixel defect, the drain terminal of the TFT 60 and the source bus line are short-circuited (hereinafter, referred to as “source-drain short-circuiting”). When the pixel defect is corrected by source-drain short-circuiting, the video signal AV on the source bus line is constantly supplied to the drain terminal of the TFT 60, allowing the display brightness of the faulty pixel portion to consistently accord with the video signal AV on the source bus line. The video signal AV is applied to the source bus line for the most of time, and therefore the faulty pixel portion is visually less recognizable as a bright spot defect.
[Patent Document 1] Japanese Laid-Open Patent Publication No. 2-204718
[Patent Document 2] Japanese Laid-Open Patent Publication No. 1-128098
[Patent Document 3] Japanese Laid-Open Patent Publication No. 6-141269